1. Technical Field
The present invention relates to power supplies and, in particular, to mechanisms for modeling the rate at which power supply voltages change in response to the current demands of integrated circuits.
2. Background Art
Over the past 25 years, power consumption by integrated circuits such as microprocessors, has grown from under one watt to over 100 watts. The dramatic increase in power is a result of transistor scaling, which has produced many more transistors on a chip running at much higher frequencies. Traditionally, voltage scaling has been used to reduce power to manageable levels. However, with supply voltages approaching one volt, further large reductions in voltage are not likely to provide additional power reduction. The following discussion focuses on microprocessors, but it will be recognized that any integrated circuits operating at high frequencies and subject to varying work loads will be subject to the similar problems.
A microprocessor that consumes 100 W requires a power supply, voltage regulator, and power distribution network capable of supplying 100 W, as well as a thermal solution (package, heat sinks, and fans) capable of dissipating the resulting heat. Such components are costly and cannot be expected to scale to higher power levels as transistor dimensions shrink.
In addition to the absolute power levels, changes in power levels are problematic. In particular, current fluctuations associated with rapid changes in power level can cause the voltage seen by a device to move outside a specified range. A hypothetical 100 W microprocessor running at 1.0V draws 100 A. To ensure proper circuit operation, a voltage regulator and power distribution network must maintain the supply voltage to within +/−5%. This means that no more than 100 mV peak-to-peak ripple can be tolerated regardless of what the microprocessor (or the software it is running) does. An ideal power distribution network will have sufficient capacitance, and small enough inductance and resistance, to maintain the supply voltage to within 100 mV even though the microprocessor's supply current may change dramatically within a few nanoseconds. This latter problem is referred to as the di/dt problem after the definition of inductance, V=L•di/dt. V is the voltage across an inductor of value L when subject to a change in current di/dt. Practical power distribution networks do not currently provide these ideal characteristics.
Mitigating the effects of di/dt on voltage levels becomes increasingly difficult as power management techniques, like clock-gating, are deployed in microprocessor designs. For example, a power-hungry unit, such as the floating-point execution unit, may be equipped with a circuit that turns on the clock when the unit is active and shuts off the clock when the unit is inactive. Clock gating may be implemented with extremely fine granularity—unit by unit and pipestage by pipestage—resulting in a large number of clock gating signals. This technique minimizes power consumption in inactive units, but it results in large variations in overall power levels that depend on the software being run.
The present invention addresses these and other problems associated with power delivery networks.